Design and Implementation of Analog Viterbi Decoder for Convolution Decoding Applications using 0.18μm Technology

With the continually increasing need for transmission of digital data over noisy channels, need for error control and correction techniques are also raising as well. There are various techniques and methods available for transmission of digital data over noisy channel but Viterbi Decoder is most efficient .It provides better coding gain at lower cost and good performance Convolutional encoding with Viterbi Decoding is a Forward Error Correction technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). In this work, a software and hardware reference model of Current Mode Analog Viterbi Decoder is presented. The design is developed for rate 1⁄2, constraint length three and speed 50 Mbits/s. The Unit Adder block has reduced from three half adders to one half adder and two ex-or gates. This modification reduces power from 0.062772 mW to 0.036130 mW. Similarly, the PMRU block of design has reduced from three half subtractors to one half subtractor and two ex-or gates. The modified design reduces power from 0.021731 mW to 0.018481 mW. The software reference model of the design is developed in MATLAB/Simulink. The hardware reference model of the design is developed in HSPICE, Virtuoso Schematic and Layout Editor. The power consumed by BMU block is 0.0171mW, PMRU block is 0.0166 mW and Unit Adder is 0.0199 mW in HSPICE. The area consumed by BMU block is 888.87 μm, PMRU block is 4135.61 μm and Unit Adder is 5240.39μm in Virtuoso Layout Editor. The complete design contains 7,500 transistors and 400329.93 μm area.